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The work presented in this paper is analysis and design of power efficient Network on Chips (NoCs). NoC architecture, routers, structure of NoC, topologies and their components has been discussed in this work. The parameters likely speed, latency, static and dynamic power is analyzed. This work found better results as compared to previous works.
Network on chips are becoming an important aspect in areas of multiprocessor chip design and high performance computing. reduction in usage of excess amount of hardware in router d...
Network on a chip is a concept in which a single silicon chip is used to implement the com-munication features of large-scale to very large-scale integration systems. for high-end ...
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