Performance analysis of various parameters of network-on-chip (noc) for different topologies

• Authors Details :  
• Ashish Mulajkar And Govind Singh Patel

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Network on a chip is a concept in which a single silicon chip is used to implement the com-munication features of large-scale to very large-scale integration systems. For high-end System on Chip de-signs, Network on Chip is considered the best integrated solution. NoC has several advantages over dedicat-ed wiring and buses i.e. increased bandwidth, low latency, less power consumption and scalability. Reduc-tion in the latency (end-to-end latency and network latency), loss probability, energy consumption and re-sponse time are the basic parameters which are considered by the researchers for the optimization of the networks-on-chip topologies. In this paper we review the most popular technologies and also some recent topologies for interconnection networks. We study their performance and summarize their strengths & weakness.

Article Subject Details

• Engineering management
• Interdisciplinary science
• Nanoparticles
• Nanotechnology

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