Performance analysis of first order digital sigma delta adc

P.a.harsha Vardhini; M.madhavilatha; C.krishna Reddy

Authors Details :
P.a.harsha Vardhini,
M.madhavilatha,
C.krishna Reddy

Journal title : 2012 Fourth International Conference on Computational Intelligence, Communication Systems and Networks

Publisher : IEEE

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Ever-growing era of mobile and personal wireless networks, motivated research in several fields of engineering resulted in low power and low cost consumer products. The voice band processing required in mobile applications demand for architectures, which can easily be integrated in single chip SoC applications. The conventional approach is to have a dedicated IC outside the digital ICs to perform analog to digital conversion. The motivation of single chip radios demand for integration of such ADC modules on digital cellular related ICs. Mixed signal design is very challenging and hence usually it is preferred to have separate ADC chip before the ASIC/FPGA. In this paper we present a digital sigma delta ADC architecture, which can perfectly be integrated in any digital IC with a targeted sampling rate of 20 kS/s with more than 80 dB dynamic range.