P.a. Harsha Vardhini

Performance analysis of first order digital sigma delta adc

  • Authors Details :  
  • P.a.harsha Vardhini,  
  • M.madhavilatha,  
  • C.krishna Reddy

Journal title : 2012 Fourth International Conference on Computational Intelligence, Communication Systems and Networks

Publisher : IEEE

888 Views Research reports

Ever-growing era of mobile and personal wireless networks, motivated research in several fields of engineering resulted in low power and low cost consumer products. The voice band processing required in mobile applications demand for architectures, which can easily be integrated in single chip SoC applications. The conventional approach is to have a dedicated IC outside the digital ICs to perform analog to digital conversion. The motivation of single chip radios demand for integration of such ADC modules on digital cellular related ICs. Mixed signal design is very challenging and hence usually it is preferred to have separate ADC chip before the ASIC/FPGA. In this paper we present a digital sigma delta ADC architecture, which can perfectly be integrated in any digital IC with a targeted sampling rate of 20 kS/s with more than 80 dB dynamic range.

Article DOI & Crossmark Data

DOI : https://doi.org/10.1109/CICSyN.2012.84

Article QR Code

Performance analysis of first order digital sigma delta adc QR Code

Article Subject Details

Article File

Full Text PDF

More Article by P.A. Harsha Vardhini

Analysis on digital implementation of sigma-delta adc with passive analog components

Sigma-delta (sd) analog to digital converters (adcs) have several advantages over the nyquist rate type adcs. the linearity over high dynamic range makes the sd adcs an ideal choic...

Optimum decimation and filtering for reconfigurable sigma delta adc

The sigma delta analog to digital converter (sd-adc) with passive analog components is presented. the digital blocks required for creating the samples with required sample rate and...