P.a. Harsha Vardhini

Optimum decimation and filtering for reconfigurable sigma delta adc

  • Authors Details :  
  • P.a.harsha Vardhini,  
  • M.madhavilatha,  
  • C.v.krishna Reddy

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The Sigma Delta Analog to Digital Converter (SD-ADC) with passive analog components is presented. The digital blocks required for creating the samples with required sample rate and word length from the 1 bit ADC output are presented. The digital filters are initially modeled in MATLAB Simulink and validated in frequency domain. Further they are synthesized to Xilinx Spartan-6 FPGA technology. The synthesis results report clock speeds up to 300MHz. The simulation results are used to validate the principle and verify the performance of SD-ADC. The results demonstrate a promising technology area of realizing SD-ADC as a reconfigurable block on FPGA to meet several signal processing applications with sampling rates up to few hundreds of KHz

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