Analysis on digital implementation of sigma-delta adc with passive analog components

P.a.harsha Vardhini; M.madhavilatha; C.v.krishna Reddy

P.a. Harsha Vardhini

Authors Details :
P.a.harsha Vardhini,
M.madhavilatha,
C.v.krishna Reddy

Journal title : International Journal of Computing and Digital Systems

Publisher : Deanship of Scientific Research

Print ISSN : 2210-142X

Page Number : 71-77

Journal volume : 2

Journal issue : 2

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Sigma-Delta (SD) analog to digital converters (ADCs) have several advantages over the nyquist rate type ADCs. The linearity over high dynamic range makes the SD ADCs an ideal choice for voice and precise instrumentation applications. The SD-ADC architecture is well established and analyzed [5, 6]. It is heavily based on digital processing and provides a high resolution, low noise output with very low analog implementation effort. The technique of sigma delta ADC is in practice from several decades. The feature of digital dominated design of SD-ADC makes it different from other types of ADCs. As the technologies are evolving, new realization methodologies are emerging for realizing SD-ADC. The conventional approach of realizing an ADC as a separate ASIC and providing the interface to digital IC (either Microprocessor or FPGA) for providing mixed signal processing platform has following limitations.