Ashish Mulajkar

3d torus router architecture for efficient network on chip design

• Authors Details :  
• Ashish A Mulajkar,  
• Govind S Patel,  
• Sanjeet K Sinha,  
• Suman L Tripathi And Sobhit Saxena

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Network on Chips are becoming an important aspect in areas of multiprocessor chip design and high performance computing. Reduction in usage of excess amount of hardware in router design without operating all parameters can improve the performance of the system. The practical review of various routers applied in future of networking is carried out in this paper. Fundamental design considerations and various components involved in router design in terms of communication, energy management and power conversion is summarized in detail. A brief comparison of various routers designed previously has been made along with design aspects for 3D Torus router.

Article Subject Details

• Engineering management
• Interdisciplinary science
• Nanoparticles
• Nanotechnology

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